1. Field of the Invention
This invention relates to electronic circuitry and, more particularly, to a communication system having a receiver that uses a built-in-self-test (BIST) circuit and method to test for and correct any cycle slip that occurs within a deserializer output of the receiver. One or more bits within a related set of bits of a serial bitstream that slip to a successive frame clock cycle are detected using two similar pseudo random bit sequences (PRBSs) received upon the receiver and generated within the receiver, and any cycle slip occurrences can be corrected by either extending the frame clock cycle or shifting the boundary between a pair of register outputs using a barrel shifter.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art or conventional by virtue of their inclusion within this section.
Communication between nodes of a communication system typically involves a serial bitstream. Examples of serial bitstream transfer protocols include Ethernet and Synchronous Optical Network (SONET), as well as numerous others. An integral part of the serialized communication between nodes is the transceiver associated with each node. A transceiver having both a receiver and a transmitter functions not only to recognize the transfer protocols, but also converts the serial bitstream to multiple bitstreams if necessary. The conversion from a relatively high bit rate serial bitstream to a set of relatively low bit rate parallel bitstreams takes place within a receiver and, more specifically, within a deserializer of the receiver.
The serializer and deserializer of the transceiver are normally found within the physical media attachment (PMA) sub-layer of the transceiver. The serializer/deserializer is responsible for supporting multiple communication protocols and allows presentation of encoding schemes to the upper layers of, for example, the Open System Interconnection (OSI) model. A useful feature of a deserializer within the physical layer PMA of the OSI model is that the deserializer can frame its output once synchronization between its serial bitstream of related bits and parallel output of related bits is achieved.
Framing is used in the normal mode to reframe data in backplane tranceivers and, as such, is an integral part of the IEEE 802.3z Gigabit Ethernet and Fibre Channel Standards set forth in http://www.ieee.org and http://www.fibrechannel.org. Framing of serial data is, therefore, the conversion of the serial bitstream to respective frames output in parallel from the deserializer. Certain bits within the serial bitstream are related to one another and thus belong within the same frame output from the deserializer.
A typical receiver within a communication system involves both a deserializer and a clock generator. The deserializer receives a serial bitstream of data broken into related sets of bits known as characters. For example, a first character of A0-A15 will be immediately followed by a second character B0-B15. Each character is preferably output from the deserializer within a single frame. Thus, in this example, all 16 character A bits are output in parallel within a single frame cycle, followed by all 16 character B bits output in parallel in the immediately succeeding frame cycle. Thus, the serial bitstream is sampled on the input of the deserializer according to a bit clock cycle, and the parallel output from the deserializer occurs every frame clock cycle. If there are 16 bits output per frame, then the frame clock cycle is equal to 16 times the bit clock cycle.
There are numerous types of deserializers known in the industry. For example, a deserializer can be formed from shift registers. As the serial bitstream is received on the shift registers, the bit clock will shift serial bits into and through the registers, and a character or frame of related bits, is captured each time the shift registers are filled, once per frame cycle. Another type of deserializer involves a staged or pipelined deserializer. A popular pipelined deserializer is described in U.S. Pat. No. 5,128,940 herein incorporated by reference. Each stage of the pipelined deserializer includes one or more 1-to-2 demultiplexer cells, where each stage can be clocked by successively slower clock rates produced by the clock generator.
Regardless of the type of deserializer used, a problem known as “bit shift” or “bit slip” oftentimes occurs. As described in U.S. Pat. No. 5,128,940, due to margin differences from one demultiplexer cell to another, related bits (A0-A15) may not necessarily appear within the same frame output simultaneously from the final stage of the deserializer. There can be many causes for the bit shift/slip problem, one such cause might be due to the uncertainty in the initial period of the signal input. There are many mechanisms for correcting a bit slip occurrence, such as applying control signals selectively to the control clocks forwarded to each stage of the pipelined deserializer. Other mechanisms can also come into play. Regardless of how a bit slip occurs or how it is corrected, it is important to be able to detect a bit that should be in one frame, yet appears in the succeeding frame.
It would be desirable to introduce a built-in-self-test (BIST) mechanism for detecting a bit slip/shift occurrence at the output of a deserializer. Moreover, the BIST architecture would benefit by being applicable to any type of deserializer, regardless of whether the deserializer is a pipelined deserializer, a shift register, or simply a programmable state machine, such as a programmable logic device or execution unit which receives software instructions.
The desired BIST architecture must also be applicable to any bit transfer rate, even the higher bit rates of SONET and Gigabit Ethernet. In addition, the desired BIST architecture must also implement bit slip/shift correction techniques in order to realign or resynchronize the frame boundaries even though a shift might occur within the deserializer. Any improvements in the BIST and error correction capabilities must be performed with minimal added complexity, design costs and architecture/layout size.